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1 for more information www.linear.com/ltc4420 typical a pplica t ion fea t ures descrip t ion 18v dual input micropower powerpath prioritizer with backup supply monitoring the lt c ? 4420 is a dual input monolithic powerpath? prioritizer, with low operating current, that provides backup switchover for keeping critical circuitry alive dur- ing brownout and power loss conditions. unlike diode-or products, little current is drawn from the inactive supply even if its voltage is greater than the active supply. internal 2, current limited pmos switches provide power path selection from a primary input ( v 1) or a backup input ( v2) to the output. tw o adjustable voltage monitors set via external resistive dividers provide flexibility in set- ting v1 to v2 switchover and v2 undervoltage thresholds. v1 is monitored continuously while v2 supply monitoring includes controllable low duty cycle uv monitoring. when primary input v1 drops, the adj monitor causes out to be switched to v2. when v2 drops, it is disconnected from out if v2dis is low. fast non-overlap switchover circuitry prevents reverse and cross conduction while minimizing output droop. auxiliary voltage monitor cmp1 provides flexible voltage monitoring and output v2ok provides v2 undervoltage status. freshness seal mode prevents v 2 battery discharge during storage or shipment. a pplica t ions n selects highest priority valid supply from tw o inputs n wide 1.8v to 18v operating range n internal dual 2, 0.5a switches n low 3.6a operating current n low 320na v2 current when v1 connected to out n blocks reverse and cross conduction currents n reverse supply protection to C15v n built-in v2 test with optional v2 disconnect n v2 freshness seal/ship mode n 1.5% accurate adjustable switchover threshold n 2.3% accurate v2 monitor and comparator n overcurrent and thermal protection n thermally enhanced 12-pin 3mm 3mm dfn and 12-lead exposed pad msop packages n low power battery backup n portable equipment n point-of-sale (pos) equipment l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. typical switchover waveforms + v1 adj v1uv v2ok typical values: switchover threshold: v1 < 4v (v1 falling) cmp1 v2 v2uv gndsw 1m 1m 1m out 237k 121k out 5v wall adapter cmpout1 v2ok v2dis v2test ltc4420 gnd 4420 ta01a 4.02m v1uv threshold: v1 < 4.4v (v1 falling) v2ok threshold: v2 < 6v (v2 falling) 7.4v li-ion 280k 10f ltc 4420 4420f 2v/div v2 2v/div 4420 ta01b switchover threshold c out = 10f i load = 100ma v2 monitoring interval v2 undervoltage and disconnect out 20ms/div v1
2 for more information www.linear.com/ltc4420 a bsolu t e maxi m u m r a t ings terminal voltages v 1, v2 ...................................................... C 15 v to 24 v out ....................................................... C0. 3 v to 24 v out C v 2 .................................................C 24 v to 39v out C v 1 ................................................. C24 v to 39v input voltages ad j , cmp 1, v2 uv , v2 test , v2 dis ( no te 3) ................................................ C 0.3 v to 24 v output voltages cmp out 1, gndsw , v2 ok ( note 3) ...... C 0.3 v to 24 v (notes 1, 2) lead free finish tape and reel part marking* package description temperature range ltc4420cdd#pbf ltc4420cdd#trpbf lgmr 12-lead (3mm 3mm) plastic dfn 0c to 70c ltc4420idd#pbf ltc4420idd#trpbf lgmr 12-lead (3mm 3mm) plastic dfn C40c to 85c ltc4420cmse#pbf ltc4420cmse#trpbf 4420 12-lead plastic exposed pad msop 0c to 70c ltc4420imse#pbf ltc4420imse#trpbf 4420 12-lead plastic exposed pad msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v1 = 3.6v, v2 = 3.6v unless otherwise noted. top view 13 gnd dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 v2 v2dis v2uv out v2ok gndsw v1 v2test cmp1 adj gnd cmpout1 6 7 t jmax = 125c, ja = 43c/w exposed pad ( pin 13) is gnd, must be soldered to pcb 1 2 3 4 5 6 v1 v2test cmp1 adj gnd cmpout1 12 11 10 9 8 7 v2 v2dis v2uv out v2ok gndsw top view 13 gnd mse package 12-lead plastic msop t jmax = 125c, ja = 40c/w exposed pad ( pin 13) is gnd, must be soldered to pcb p in c on f igura t ion pin currents ( note 2) ad j , cmp 1, v2 uv , cmpout 1, gndsw ............. C1 ma v2 tes t , v2 dis , v2 ok ...................................... C1 ma op erating ambient temperature range ltc 4 420 c ................................................ 0 c to 70 c ltc 4 420 i ............................................. C 40 c to 85 c junction temperature ( notes 4, 5) ........................ 12 5 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ms op package ................................................. 300 c symbol parameter conditions min typ max units supply voltage and currents v1, v2 operating voltage range l 1.8 18 v i v1 v1 current, v1 powering out v1 current, v2 powering out i out = 0, v1 = 8.4v, v2 = 3.6v v1 = 8.4v, v2 = 3.6v l l 3.6 500 6.3 800 a na o r d er i n f or m a t ion (http://www .linear.com/product/ltc4420#orderinfo) ltc 4420 4420f
3 for more information www.linear.com/ltc4420 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: these pins can be tied to voltages down to C5v through a resistor that limits the current to less than C1ma. note 4: the ltc4420 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5: the ltc4420 is tested under pulsed load conditions such that t j t a . the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v1 = 3.6v, v2 = 3.6v unless otherwise noted. symbol parameter conditions min typ max units i v2 v2 current, v2 powering out v2 current, v1 powering out v2 current in freshness seal mode i out = 0, v1 = 3.6v, v2 = 8.4v v1 = 3.6v, v2 = 8.4v v1 = gnd, v2 = 5v l l l 3.3 320 120 6 650 220 a na na r on switch resistance v1 = v2 = 5v, i out = C100ma l 1 2 5 t valid(v1) input qualification time v1 rising, adj rising l 34 64 94 ms input comparators v tha adj threshold adj falling l 1.032 1.047 1.062 v v hysta adj comparator hysteresis adj rising l 30 50 70 mv v thc cmp1, v2uv threshold cmp1, v2uv falling l 0.378 0.387 0.396 v v hystc cmp1, v2uv comparator hysteresis cmp1, v2uv rising l 7.5 10 12.5 mv t pda adj comparator falling response time 10% overdrive l 4 7.3 12 s t pdc cmp1, v2uv comparator response times 20% overdrive l 30 65 s power path function i lim output current limit v1, v2 = 8.4v l 0.5 1.1 1.6 a v rev reverse comparator threshold (v1, v2) C v out for power path turn-on l 25 50 75 mv t switch break-before-make switchover time v1 = v2 = 5v, i out < 10ma l 1 2.5 5 s v2 monitoring t monl longest possible v2uv monitor duration v2test v ih l 88 128 168 ms t mons shortest possible v2uv monitor duration v2test v ih l 1 2 3 ms t ltest time between v2uv monitoring events v2test v ih l 80 132 180 s t hv2t minimum allowed v2test high time v2test driven externally l 10 ms t lv 2t minimum allowed v2test low time v2test driven externally l 10 ms i/o specifications v ol output voltage low, cmpout1, gndsw and v2ok i = 100a i = 1ma l l 15 120 50 250 mv mv v oh v2ok output high voltage i = C1a, v2 = 5v l 1.05 1.65 2.3 v i oh v2ok, gndsw, cmpout1 output high leakage cmpout1, gndsw, v2ok = 18v l 50 150 na v il v2dis , v2test input low voltage v1 = v2 = 5v l 0.2 v v ih v2dis , v2test input high voltage v1 = v2 = 5v l 0.9 v i v2x(in,z) v2dis, v2test allowable leakage in open state l 0.5 a i pu(v2ok) v2ok pull-up current v2 = 5v, adj = 0v, v2ok = 0v l C2.7 C5 C8 a i leak adj, cmp1, v2uv leakage current adj, cmp1, v2uv = 0v, 1.5v l 1 5 na ltc 4420 4420f
4 for more information www.linear.com/ltc4420 typical p er f or m ance c harac t eris t ics v1 current, v1 powers out (i out = 0) v2 current, v2 powers out (i out = 0) v2 current, v1 powers out (t a = 25c, v1 = v2 = 3.6v unless otherwise indicated) v1 current, v2 powers out normalized falling adj threshold vs temperature normalized cmp1 and v2uv falling thresholds vs temperature adj hysteresis vs temperature adj leakage vs temperature open-drain (cmpout1, gndsw, v2ok) v ol vs pull-down current v1 current (na) ltc 4420 4420f 125 1.010 normalized v tha 4420 g07 temperature (c) ?50 ?25 0 25 50 0.990 75 100 125 30 40 50 60 70 adj hysteresis (mv) 4420 g08 0.995 v adj = 0v, 1.5v temperature (c) ?50 ?25 0 25 50 75 100 125 1.000 0.5 1.0 1.5 2.0 2.5 3.0 adj leakage (na) 4420 g09 v2 = 1.8v v2 = 3.6v 1.005 v2 6v temperature (c) ?50 ?25 0 25 50 75 100 125 1.010 2.5 3.0 3.5 4.0 v2 current (a) 4420 g02 normalized v thc 4420 g06 v1 = 1.8v v1 = 3.6v temperature (c) v1 6v temperature (c) ?50 ?25 0 25 50 75 100 125 ?50 2.5 3.0 3.5 4.0 4.5 v1 current (a) 4420 g01 v1 = v2 ?40c 25c ?25 90c v2 voltage (v) 0 5 10 15 20 150 200 250 0 300 350 400 450 v2 current (na) 4420 g03 v1 = v2 ?40c 25c 90c 25 v2 voltage (v) 0 5 10 15 20 300 350 400 450 50 500 550 4420 g04 pull-down current (ma) 0 0.5 1 1.5 2 0 75 50 100 150 200 250 v ol (mv) 4420 g05 temperature (c) ?50 ?25 100 0 25 50 75 100 125 0.990 0.995 1.000 1.005
5 for more information www.linear.com/ltc4420 v1 reverse voltage blocking with v2 powering out typical p er f or m ance c harac t eris t ics switch r on vs temperature i out vs v out for different input supply voltages output current limit vs temperature switchover from a higher to a lower voltage freshness seal current vs v2 voltage and temperature output voltage and current waveforms during switchover output current i out response for different shorting impedances (t a = 25c, v1 = v2 = 3.6v unless otherwise indicated) ltc 4420 4420f 125 6v 10s/div v2 i out 0.5a/div v1 2v/div 4420 g16 i load = 50ma 0.80 6v ?10v 10v 20ms/div v2 5v/div v1 10v/div i out 0.5a/div 0.90 4420 g17 1.2 2.2 3.3 3.9 5 40s/div 0 0.5 1.0 1.00 1.5 2.0 2.5 3.0 i out (a) 4419 g11 1.10 1.20 1.30 1.40 current limit (a) 4420 g10 temperature (c) ohmic current limit foldback v in = 1.8v v in = 3.6v v in = 5v v out (v) 0 1 2 ?50 3 4 5 0 0.2 0.4 0.6 0.8 1.0 1.2 ?25 i out (a) 4419 g12 5v 3.6v 2v temperature (c) ?50 ?25 0 25 0 50 75 100 125 1 2 3 4 5 r on () 25 4419 g13 v1 = 0v 1.8v 3.6v 5v 6v temperature (c) ?50 ?25 0 50 25 50 75 100 0 50 100 150 200 250 75 v2 current (na) 4420 g14 c out = 10f i out = 200ma disconnect from v1 connect to v2 3ms/div v1 out 2v/div v2 100 4419 g15 c out = 10f i load = 50ma c1= c2 = 10f out 10v
6 for more information www.linear.com/ltc4420 p in func t ions adj: adjustable switchover threshold input. adj is the noninverting input to the switchover threshold comparator. if v 1 1.55 v and adj 1.097 v for at least 64 ms, out is switched internally to the primary v1 input. when the adj input voltage is lower than 1.047 v, out is switched internally to v2 if conditions in table 1 of the applica - tions information section are met. otherwise, out stays unpowered. tie adj via a resistive divider to v1, in order to set the v1 to v2 switchover voltage. do not leave open. cmp1: auxiliary comparator 1 monitor input . cmp1 is the noninverting input to an auxiliary comparator. the invert - ing input is internally connected to a 0.387 v reference. connect cmp1 to gnd when it is not used. cmpout1: auxiliary comparator output 1. this open- drain comparator output is pulled low when cmp1 is below 0.387v and during power-up, otherwise it is released. once released, connecting a resistor between cmpout1 and a desired supply voltage up to 18 v causes this pin to be pulled high. leave open if unused. gndsw: pulsed gnd output. this open-drain output is pulled low when v2uv is being monitored, otherwise it is released high. connect a resistive divider between v2, v 2uv and gndsw to set v2 undervoltage threshold. leave open if unused. exposed pad: for best thermal performance, solder the exposed pad to a large pcb area. gnd: device ground. out: output voltage supply. out is a prioritized voltage output that is either connected to v1, v2 or is unpowered as indicated in table 1 of the applications information sec - tion. additionally, out must be at least 50 mv below the input supply for a connection to that supply to be activated. bypass with a capacitor of 1 f or greater. see applica - tions information for bypass capacitor recommendations. v1: primary power supply. out is internally switched to v1 if v 1 1.55 v and adj 1.097 v. when in freshness seal, applying v 1 1.55 v and adj 1.097 v for 32ms disables freshness seal. bypass with 1 f or greater. tie to gnd if unused. v2: backup power supply. out is internally switched to v2 if adj < 1.047 v or v1 < 1.55 v, provided other condi - tions listed in table 1 in applications information are met. bypass with 1f or greater. tie to gnd if unused. v2dis: v2 power path disable input. when driven low, this pin disables the v2 to out power path if input v2uv drops below 0.387 v. connect a resistor between v2 or out and this pin to provide additional pull-up. leave open if unused. this pin is initialized high during power-up. v2ok: v2ok logic output. v2ok is an output that is driven high with a 5 a pull-up if v2uv > 0.387 v at the end of the v2uv monitoring period. otherwise it is driven low. connect a resistor between out and this pin to provide additional pull-up. as this pin is used to enable freshness seal, do not force low or connect a pull-down resistor to this pin. leave open if unused. v2test: v2 undervoltage test enable input. this pin sets the duty cycle of v2 undervoltage monitoring. when v1 is valid, driving v2test low disables v2 monitoring while driving it high enables v2 monitoring with a maximum duty cycle of ~0.1%. when v1 is invalid or not present, v2 is always monitored with v2test setting the duty cycle between 0.0015% and 0.1% depending on its own state and previously determined v2 validity. refer to the state diagram and waveforms in the applications informa - tion section for details. leave open or connect a resistor between v2 or out and this pin to provide additional pull-up. connect to gnd if unused. this pin is initialized high on power-up. v2uv: v2 undervoltage monitor input. v2uv is the non - inverting input to a comparator whose inverting input is internally connected to a 0.387 v reference. connect a resistive divider between v2, v2uv and gndsw to set v2 undervoltage threshold. see the applications information section for details on v2 monitoring. connect a pull-up resistor to v2 if unused. do not leave open. ltc 4420 4420f
7 for more information www.linear.com/ltc4420 func t ional diagra m + ? + ? + ? + ? 0.397v/ 0.387v cp1 cmp1 v2 v1 en1 cuv1 cuv2 1.55v/ 1.52v en2 50mv crev2 5a 2.5v out cmpout1 v2ok control logic gndsw en_gndsw + ? + ? 50mv crev1 + ? 6 3 1 12 9 8 7 freshness seal + ? 1.097v/ 1.047v 1m cadj 64ms 7.3s adj 4 + ? 0.397v/ 0.387v cv2uv v2uv 10 v2dis 11 1m v2test 2 gnd 5 d q e 4420 bd ltc 4420 4420f
8 for more information www.linear.com/ltc4420 o pera t ion the functional diagram shows the major blocks of the ltc4420. the ltc4420 is a powerpath prioritizer that switches output out between primary ( v1) and backup (v2) sources depending on their validity and priority with v1 having the highest priority. a resistive divider between v1, adj and gnd and comparators cuv1 and cadj are used to monitor v1s voltage to establish validity. v1 is valid if v 1 1.55 v and adj 1.097 v for 64 ms after v1 rises above 1.55 v. otherwise v1 is invalid. a resistive divider between v2, v2uv and gndsw and comparators cuv2 and cv2uv are used to monitor v2s voltage to establish validity. v2 voltage is monitored periodically in order to minimize current consumption in the divider. v2 is valid if v 2 1.55 v and v2uv 0.4 v at the end of the v2 monitoring period. otherwise it is invalid. if neither supply is valid, out stays unpowered if v2dis is low. if v2dis is high and v2 > 1.55 v, out is connected to v2. refer to table 1 in the applications information section for details. switchover threshold is independent of relative v1 and v2 voltages, permitting v1 to be lower or higher than v2 when v1 powers out and vice versa. power connection to the output is made by enhancing back- to-back internal p-channel mosfets. current passed by the mosfets is limited to typically 1.1 a if out is greater than 1 v. otherwise it is limited to 250 ma. when switching from v1 to v2, the v1 to out power path is first disabled and comparator crev2 is enabled. after the out voltage drops 50 mv below v2, as detected by crev2, out is then connected to v2. this break-before-make strategy prevents out from backfeeding v2. switchover back to v1 occurs in a similar manner once v1 has been revalidated. the ltc4420 blocks reverse voltages up to C15 v when a reverse condition occurs on an inactive channel. the ltc4420 also disables a channel if the corresponding input supply falls below 1.52 v. a small ~3 a current is drawn from either the prioritized input supply, or the high - est supply if both input supplies are below 1.55v. ve ry little current (~320 na) is drawn from the unused supply. pins v2test and v2dis provide flexibility in monitoring and disconnecting the v2 power path using the v2uv monitor input. v2 is monitored by activating the v2-v2uv- gndsw resistive divider. v2test allows for adjustability of gndsw duty cycle to trade off v2 quiescent current with v2 monitoring frequency. when low, v2dis disables the v2 to out power path, if v2 is found to be invalid. refer to the applications information section for details. if v2 is valid at the end of a v2 monitoring interval, output v2ok is latched high. otherwise it is latched low. v2ok retains its state until the end of the next v2 monitoring interval when it gets updated. v2 monitoring is disabled if v 2 < 1.55v or during thermal shutdown. during initial power- up v2 monitoring is disabled and v2ok is initialized low. the ltc4420 provides an additional comparator, cp1, whose open-drain output pulls low either when the cmp1 pin voltage falls below 0.387 v or during initial power up. this comparator can be used to monitor supplies to provide early power failure warning and other useful information. the ltc4420 can be put into a v2 freshness seal mode to prevent battery discharge during storage or shipment. the applications information section lists the steps to engage and disengage v2 freshness seal. ltc 4420 4420f
9 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion the ltc4420 is a low quiescent current 2- channel priori- tizer that powers both its internal circuitry and its output out from a prioritized valid input supply. unlike an ideal diode-or, the ltc4420 does not necessarily draw current from the highest supply as long as one supply is greater than 1.8 v. table 1 lists the input supply from which the ltc4420 draws its internal quiescent current i cc and the supply to which out is connected after input supplies have been qualified. a typical battery backup application is shown in figure 1. v1 is powered by a 2- cell li-ion battery pack whose safe discharge limit is between 5.6 v and 6 v. v2 is powered by a low self discharge 7.6 v li-thionyl chloride (li-socl 2 ) hold-up battery which is completely discharged when its voltage drops to 6 v. li-socl 2 battery life is maximized as very little current is drawn from v2 during normal operation due to the low duty cycle of v2 monitoring and the ltc4420s low v2 standby current. to protect the 2-cell li-ion battery on v1, switchover threshold is set to be ~5.6 v. after switchover to v2, the li-ion battery primarily supplies only divider r1-r3s current as the ltc4420 draws only a small standby current from v1. monitor cmp1 is configured to provide v1 power failure warning by driving v1uv low when v1 falls below 6v. monitor input v2uv is configured to set v2s uv threshold to 6 v and v2dis is tied low to disconnect the v2 to out power path when v2 falls below 6 v. v2test is tied high to monitor v2 once every 132 s. relevant equations used to calculate these component values are discussed in the following subsections. figure 1. the ltc4420 protecting 2-cell lithium battery packs on v1 and v2 from discharge below their safe minimum voltage setting switchover and v2 undervoltage thresholds several factors affect switchover voltage and should be taken into account when calculating resistor values. these include resistor tolerance, 1.5% adj comparator threshold error, divider impedance and worst-case adj pin leakage. these factors also apply to resistive dividers connected to monitor inputs cmp1 and v2uv. referring to figure 1 and the electrical characteristics table, the typical v1 switchover threshold: v sw1 = v tha r1 + r2 ? r1 + r2 + r3 ( ) (1) table 1. out and ltc4420 i cc power input voltages v1 > 1.55v adj > 1.097v v2 > 1.55v v2dis > 0.9v v2uv > 0.397* i cc source out connection y ? y ? x x x v1 v1 y n y y x v2 v2 y n y n y v2 v2 y n y n n v1 hi-z y n n x x v1 hi-z n x y n n v2 hi-z n x y n y v2 v2 n x y y x v2 v2 n x n x x v max ** hi-z *note: refers to v2uv voltage at the end of the v2 monitoring period. **note: v max = higher of v1 and v2. ? for 64ms. + v1 adj cmp1 v2uv v1uv v2 v2uv gndsw 4420 f01 r3 1m v1uv : v1 < 6v (v1 falling) v2uv : v2 < 6v (v2 falling) r6 1m r7 1m r8 1m c out 10f r2 150k r1 78.7k out out v2test v2ok cmpout1 v2dis ltc4420 gnd r5 4.02m switchover threshold: v1 < 5.6v (v1 falling) + 2-cell li-ion 7.4v 2-cell li-socl 2 7.4v r4 280k c1 4.7f c2 4.7f ltc 4420 4420f
10 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion typical v1 undervoltage threshold is: v v1uv = v thc r1 ? r1 + r2 + r3 ( ) (2) worst-case v ol due to current flow into the gndsw pin must be taken into account while calculating values for the v2 undervoltage resistive divider: v v2uv = v thc r4 + v ol 100a ? r4 + r5 + v ol 100a ? ? ? ? ? ? (3) equations 1-3 assume adj and cmp1 pin leakages are negligible. to account for pin leakage, equations 1-3 must be modified by an i leak ? r eq term where equivalent resistance r eq must be calculated on a case-by-case ba- sis. worst-case component values and reference voltage tolerances must be used to calculate the maximum and minimum threshold voltages. for example, to calculate minimum falling switchover threshold voltage v sw1(min) , use v tha(min) , (r2+r1) (max) , r3 (min) in equation 1. figure 2. adj comparator propagation delay as a function of slew rate; t pda vs dv adj /dt where i out is the current supplied by c out during non- overlap or dead time, t nov . choosing: c out t nov ? i out ? v out (5) limits output droop to less than ?v out . in order to estimate t nov and i out , first consider a scenario where power supplies are present on v1 and v2, and their voltages are changing slowly compared to the adj com - parator propagation delay t pda . for such cases, i out is i load and t nov is t switch . c out can be sized according to equation 5 with i out = i load(max) and t nov = t switch(max) to limit maximum output droop when switching to a higher supply. when switching to a lower supply, switchover is initiated only after out falls v rev below the supply that is being switched in. in such cases, total output droop is ?v out + v rev . next consider a scenario where the input power source powering out is unplugged. out backfeeds circuitry connected to the input supply pin. both input and output droop at the same rate. referring to figure 1, assume the battery on v1 is unplugged when out is connected to v1. i out is the sum of i load and the back fed current i back , which in this example is i r3 . as out and v1, since the two are connected, droop below the adj threshold , switchover occurs to v2 with a dead time t nov = t pda + t switch (6) where t pda is an overdrive dependent adj comparator delay. as an approximation, use t pda from the electrical characteristics table to estimate t nov . use this t nov and: i out = (i back + i load ) (7) in equation 5 to size c out : c out t pda + t switch ( ) ? i out ? v out (8) refer to figure 2 for a more accurate estimate of t pda vs dv out / dt. if adj is filtered with capacitor c adj , its discharge time via divider r 1 C r3 increases t pda . this results in a higher output droop than estimated by equation (8). selecting output capacitor c out c out can be selected to control either output voltage droop during switchover or output rising slew rate during initial power-up or when switching to a higher supply. in general, output droop, v out , can be calculated by: v out = t nov ? i out c out (4) ltc 4420 4420f 50 75 100 125 t pda (s) 4420 f02 dv adj /dt (v/s) 10 100 1k 10k 100k 0 25
11 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion in order to limit output rising slew rate dv out /dt, size: c out i lim dv out dt (9) as the ltc4420 limits out charging current to i lim until out approaches the input supply to within i lim ? r on , where r on is the channel switch resistance. refer to the thermal protection and maximum c out section to deter- mine maximum allowed c out . inductive effects parasitic inductance and resistance can impact circuit performance by causing overshoot and undershoot of input and output voltages when the ltc4420 turns off. parasitic inductance in the power path causes positive- going overshoot on the input and a negative-going undershoot on the output. another cause of positive input overshoot is r-l-c tank ringing during hot plug of an input supply. input overshoot is most pronounced when the total resistance of the input tank is low. care must be taken to ensure over voltage transients do not exceed the absolute maximum ratings of the ltc4420. additionally, parasitic resistance and inductance can cause input undershoot ( droop) during power path turn on. if severe enough, undershoot can temporarily invalidate a supply and cause repeated power up cycles ( motorboating) or unwanted switchover between sources. the first step to avoid these issues is to minimize parasitic inductance and resistance in the power path. guidelines are given in the layout section for minimizing parasitic inductance on the printed circuit board ( pcb). external to the pcb, twist the power and ground wires together to minimize inductance. second, use a bypass capacitor at the input to limit input voltage overshoot during ltc4420 power path turn off. a few micro farads is sufficient for most applications. when hot plugging supplies with large parasitic inductances, it is possible for the r-l-c tank to ring to more than twice the nominal supply voltage. wall adapters and batteries typically have enough loss ( i.e . series resistance) to prevent ringing of this magnitude. however, if this is a problem, snub input capacitor c sn1 with resistor r sn1 , typically 0.5. place this network close to the supply pin. third, if an input capacitor is not permissible, use a tvs (such as smaj16ca) in applications when supply pin transients can exceed 24 v. use a bidirectional tvs in applications requiring reverse input protection. note that a tvs does not address droop and motorboating, which are solved only by input bypassing. during normal operation, the ltc4420 limits power path current to < 1.6 a and internal circuitry prevents out from ringing below ground during power path turn off. this is also true for output shorts when the short is close to the ltc4420s out pin. however, if the output is shorted through a long wire, current in the wire inductance (l par2 in figure 3) builds up due to the discharge of c out1 and can be much higher than 1.6 a. this current causes the out pin to ring below its ?0.3 v absolute maximum rating once c out1 has been fully discharged. for this special case, split the output capacitor between c out1 and c out2 and make c out1 small. snub c out1 with resister r sn2 to damp r-l-c ringing if required. size c out2 to obtain the required total output capacitance. also add a diode between out and ground close to the ltc4420 to clamp negative ringing if the out pin rings below C0.3v. figure 3. recommended inductive transient suppression circuitry v1 out 4420 f03 c out1 1f d1 1n5818 c sn1 5f r sn1 0.5 l par1 optional l par2 out v1 ltc4420 r sn2 1 optional c out2 10f ltc 4420 4420f
12 for more information www.linear.com/ltc4420 v2 monitoring and control the ltc4420 monitors v2 voltage through an external resistive divider connected between v 2, v2 uv and gndsw. when v2 is being monitored, open-drain output gndsw is pulled low to activate the resistive divider, otherwise it is released high. v2uv is monitored by comparator cv2uv, whose output is latched at the end of the moni- toring period. this latched output establishes v2 validity and is used in t able 1. a pplica t ions i n f or m a t ion figure 4. state diagram describing v2 monitoring v2 monitoring duration and time between monitoring events are set by input v2test, v1 validity and v2 validity as determined previously. complete behavior is described by the state diagram shown in figure 4. this implementa- tion was chosen for the following reasons, 1. to provide flexibility in monitoring and disconnect- ing the backup battery as required by the application, while minimizing current draw through the v2 resistive divider. v2test and v2dis need to be actively driven to achieve this. v1 valid v2test high and and v2 not valid v1 valid v2test high and and v2 not valid v2 not valid and v1 not valid v2test high and v2 valid v2test low and v1 valid and v2 not valid v1 not valid v2test low and v1 valid v2test high and v2 valid v2test high and v2 not valid v2test high and v2 valid disable v2 monitoring switchover to v2 exit thermal shutdown or v1 not valid and (v2test low and v2 not valid) v1 valid and v2test low v2 valid or v2test high v2 not valid or and v2test low v1 not valid power up thermal shutdown v2 < 1.55v v2 not uv or or 128ms v2 monitoring 2ms v2 monitoring when v1 is valid wait for rising v2test or override condition 2ms v2 monitoring when v1 is invalid v1 valid and (vtest high and v2 not valid) v2test low and v1 valid 4420 f04 ( ) ltc 4420 4420f
13 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion 2. to provide default battery backup monitoring and dis- connect in systems where v2test and v2dis are not actively driven. v2test and v2dis are either tied high or low in these applications. 3. to allow a system powered by out to shut itself down if there is no valid input supply. 4. to support backup battery charging without having to disconnect the battery from the system. 5. handling exceptions such as initial power up, recov - ery from thermal shutdown and switchover after long inter vals when v2 was not being monitored. configuring v2test and v2dis v2test controls the duration of and the time between v2 monitoring events. it can either be tied high, low or actively driven based on the application. the following section explores common scenarios. in applications where primary supply v1 is going to be valid for long periods of time and where v2test can be actively driven, v2 test should generally be driven low and only pulsed high when v2 status is needed. this minimizes v 2- v2 uv- gndsw divider current. this scenario also applies when v2 is a battery that slowly discharges over time, making a v2 status update every 132 s super fluous. when operating off v2, v2test may be pulsed at intervals shorter than 131 s to check v2s validity especially after large load current spikes. if v2test cannot be actively driven, it should be tied to either v2 or out through a pull-up resistor. if v2 can be reversed, tie v2test to out. tying v2test high ensures that v2 is monitored every 132 s as long as v2 > 1.55v. v2 monitoring duration is 128 ms when v2 is valid and reduces to 2 ms if v2 becomes invalid. use smaller resis - tors in the v2-v2uv-gndsw divider if v2 is a battery that can develop a passivation layer when it is not being used. larger v2 current helps break the passivation whenever the v2 divider is active. in special cases where v2 needs to be monitored only when v1 goes invalid and when battery passivation is not an issue, tie v2test low. if automatic v2 disconnect is desired when a v2 uv event occurs, tie v2dis low. otherwise leave open or tie to either out or v2 through a pull up resistor. if v2 can be reversed, tie v2dis to out. if v 2dis can be actively driven, driving it low some time after a v2 uv event ( output v2ok goes low) allows systems powered by out to finish active tasks, backup data and initiate shutdown proceedings. actively driving v2test in figure 5, v2test is actively driven. when v1 powers up above switchover threshold v sw1 , it is qualified for 64 ms after which the v1 to out power path is activated. when v2 rises above 1.55 v, gndsw is pulsed low for 128ms and v2uv is monitored, even though v2test is low. v2 is found to be valid resulting in v2ok being driven high. as long as v1 remains valid, v2 is monitored only when v2test is driven high with v2 monitoring time being the lower of either the v2test high time or 128 ms. figure 5 shows two such monitoring events of durations t1 and t2 where t1 and t2 are less than 128 ms. when v1 drops below v sw1 , out is switched to v2 and v2 validity is refreshed by monitoring it once for 128 ms independent of the state of v2test. following this, since v2 is the only valid supply, v2 is monitored for 2ms every 132s if v2test is low or for 128 ms every 132 s if v2test is high. if v2 becomes invalid and v2dis is low, the v2 to out power path gets disabled. v2test tied low figure 6 shows voltage waveforms for the case where v2test is tied low. when v2 powers up above 1.55v, gndsw is pulsed low and v 2 is monitored once for 128ms. simultaneously, the v2 to out power path is activated in order to allow a system powered by out to power itself up and drive v2dis to a desired state. v2 is determined to be valid causing v2ok to be driven high and the v2 power path to remain activated. if v2 was determined to be invalid and v2dis was low, v2s power path would have been disabled and v2ok pulled low after 128 ms. since both v1 and v2test are low, v2 is monitored for 2ms every 132 s. when v1 becomes valid, out is switched to v1 and v2 monitoring is halted until v1 becomes invalid. ltc 4420 4420f
14 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion figure 6. v2 monitoring when v2test is low figure 5. v2 monitoring by actively driving vtest. note that t1 and t2 are < 128ms t1 t1 t2 t2 v sw1 v1 v2 v2test gndsw v2ok out 1.55v v uv2 v sw1 time 4420 f05 ~64ms v1 power path active v2 power path active 2ms 131s 128ms 128ms gndsw v2ok out v2 1.55v v2 power path active v1 power path active 128ms v uv2 v sw1 v1 131s 131s 2ms time 4420 f06 2ms ~64ms ltc 4420 4420f
15 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion increasing cmp1 hysteresis in some applications, built in cmp1 hysteresis may be insufficient. in such cases, cmp1 hysteresis can be in - creased as shown in figure 7. hysteresis at the monitored input vmon with r8 present and assuming r 9 << r8, is given by: v hyst = v hystc r3 r1||r3||r8 + v pu r3 r8 (10) where v hystc is found in the electrical table and is typi- cally 10 mv. account for supply v pu and resistor r8 when calculating rising and falling thresholds of monitored input v mon . referring to figure 1, in order to prevent switchover when c out is being initially charged add input capacitor c1. ideally, if v1 is greater than switchover threshold v sw1 by ?v, size: c1 > v sw1 ? c out ? 1C ? v 2 ? i lim ? r esr ? ? ? ? ? ? ? v (13) to ensure no switchover occurs when c out is initially be- ing charged . if the resulting c1 value causes large inrush current, is physically too big or requires a large snubber resistor when v 1 is plugged ( refer to the typical applications section), select c1 to be as high a value as the application can tolerate. a filter capacitor c adj can also be added to adj, to ride through the initial output charge up time. c adj should be minimized as it slows adj response, resulting in a larger output droop when the input supply powering v1 is either unplugged or drops quickly. input shorts and supply brownout the ltc4420 temporarily turns off its active power path during input shorts or brownout conditions if the input supply falls below out by 0.7 v. if the primary input supply becomes invalid, switchover to the backup supply occurs. the power path is reactivated when the input recovers to within 0.7v of the output. figure 8 shows the response of the ltc4420 to a brown - out and recovery on v1 where switchover to v2 does not occur as v1 stays above 1.8 v. when v1 falls, out gets disconnected from v1 and is slowly discharged by load resistance r out . when v1 recovers, the power path is reactivated and out tracks v1. in figure 9, when v1 falls, out gets disconnected from v1 as v1 drops below the switchover threshold. when v1 recovers, it needs to be qualified for 64 ms before it is reconnected to out. out gets discharged by r out and is connected to v2 once its voltage is 50mv less than v2. figure 7. increasing comp1 hysteresis cmp1 v pu 4420 f07 r3 r1 r8 cmpout1 vmon ltc4420 r9 supply impedance and adj comparator hysteresis in some applications, v1 could be supplied by a battery pack with high esr or through a long cable with appreciable series resistance. load current, i out , flowing through this resistance reduces the monitored v1 voltage by: ?v1 = i out ? r esr (11) the drop can be as high as: v1 = i lim ? r esr (12) when c out is initially being charged. voltage droop at the v1 pin can result in repeated switchover between v1 and v2 if built-in v1 (adj) hysteresis is insufficient. ltc 4420 4420f
16 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion reverse voltage blocking the ltc4420 blocks reverse voltages on supply pins v1 and v2 up to C15 v relative to gnd and up to C39 v relative to out. transient voltage suppressors ( tvs ) connected to v1 and v2 must be bidirectional and capacitors connected to these pins must be rated to handle reverse voltages. a reverse voltage on v2 does not disrupt v1 operation and vice-versa. freshness seal mode freshness seal mode prevents v2 battery discharge by keeping v2 disconnected from out even if v1 is absent or invalid. very little current is drawn from v2typically just 120 na. the following sequence ( refer to figure 10) puts the ltc4420 in freshness seal mode: 1. power up v2 and v2uv. 2. once v2ok is asserted high, drive it below 50mv. 3. power up v1 and adj for at least 94 ms. complete steps 2 and 3 within 80 s of v2ok asserting high. freshness seal is enabled. figure 9. voltage waveforms when a brownout on v1 results in switchover to v2. switchover threshold = 3v figure 8. voltage waveforms during a brownout on v1 that does not result in switchover to v2. switchover threshold = 1.8v figure 10. freshness seal engage procedure engage this mode if v2 is a backup battery either during storage or during shipment. once freshness seal has been engaged, if v1 is disconnected, v2 stays disconnected from out. freshness seal is automatically disabled the next time v1 is revalidated. limit v2ok pin capacitance to less than 10 nf in order to prevent freshness seal mode from accidentally being engaged. design example in figure 11, the ltc4420 prioritizes between a 5 v supply connected to v1 and a 7.4v 2- cell li-ion battery con - nected to v2. the system is designed to switch out to v2 when v1 drops below 4v, provide early power failure warning when v1 drops below 4.5 v and disconnect the backup battery voltage when it drops below 6 v. maximum anticipated load current is 100 ma and maximum allowed output droop is 100 mv. output rising slew rate is limited to <0.1v/s and v1 and v2 input capacitances are limited to 10f to avoid large inrush current . 1% tolerance resistors are used adj, cmp1 and v2uv pin leakages and gndsw v ol are ignored as their design impact is small. v2uv v2ok v1 adj v2 1.8v 0.48v 1.8v 1.116v 4420 f10 94ms fseal enabled driven low externally < 80s 1 2 3 ltc 4420 4420f 5v/div 4420 f08 100s/div v1 5v/div v2 5v/div out 5v/div 4420 f09 c out = 10f c out = 10f r out = 100 r out = 100 100s/div v1 5v/div v2 5v/div out
17 for more information www.linear.com/ltc4420 figure 11. design example a pplica t ions i n f or m a t ion r 1= v thc ? r1 + r2 + r3 ( ) v pfv1 (18) r1 = 0.387v 4.5v t 500k ? ( ) (19) solving equations 16 and 19 results in r1= 43.3 k and r2 = 87.6 k. using the nearest 1% resistors results in r2 = 88.7 k. recalculating equation 1 using calculated r2 and r3 values and using standard 1% resistor values close to 43.3k for r1 results in r1= 44.2k. a similar procedure is used to calculate r4 and r5 using equation 3 and total divider current. resistance of the gndsw pull-down, typically 120, is neglected as it is small compared to r4 and r5. the design equations are shown below. r4 + r5 = 7.4v 5a = 1.48m ? (20) as desired current in the divider is 5a. rewriting equation 3 neglecting pin leakage and assuming r5>>r4 results in: r4 = v thc t r4 + r5 ( ) v v2uv (21) r4 = 0.387v t 1.48m ? 6v (22) solving equations 20 and 22 results in r4 = 96.2 k and r5 = 1.38 m. choosing the nearest 1% resistor results in r4 = 95.3k and r5 = 1.37m. c out affects both out droop during switchover as de- termined by equation 4 and out rising slew rate as de- termined by equation 9. calculate minimum c out required to meet desired output droop and slew rate specifications using equations 8 and 9 and size c out to be the larger of the two values. first choose total resistive divider current to be ~10 a for v1 and 5 a for v2. since the v2 divider is pulsed with a maximum duty cycle of 0.1%, average v2 divider current is negligible. for the 5v supply, this results in: r1 + r2 + r3 = 5v 10a = 500k ? (14) since desired switchover threshold, v sw1 , and total divider impedance are known, use equation 1 to first calculate r3. using r3 and equation 2, calculate r1 and r2. rewriting equation 1 results in: r1 + r2 ( ) = v tha t r1 + r2 + r3 ( ) v sw1 (15) using ( r1+r2+r3) = 500 k from equation 14, results in: r1 + r2 ( ) = 1.047v t 500k ? 4v = 130.9k ? (16) r3 ~ (500k C 130.9k) = 369.1k (17) using the nearest 1% resistor value yields r3 = 365k. rearranging equation 2, results in: v1 adj cmp1 v2uv pfv1 v2 v2uv gndsw gnd 4420 f11 r3 365k 5v input 2-cell li-ion 7.4v r sn1 0.5 r6 1m r7 1m c out 15f r2 88.7k r1 44.2k out out v2test v2ok cmpout1 v2dis ltc4420 r5 1.37m r4 95.3k c1 2.2f c2 2.2f + ltc 4420 4420f
18 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion c out required to limit out droop to < 100 mv is given by equation 8, c out t pda + t switch ( ) ? i load 100mv (23) c out 7.3s + 2.5s ( ) ? 0.1a 100mv = 9.8f (24) c out required to limit out slew rate to < 0.1 v/s is given by equation 9, c out i lim 0.1v/s = 11f (25) choose a c out capacitor whose minimum value is 11f accounting for voltage and temperature coefficients. do this for other capacitors as well. assuming correct pcb figure 12. recommended 12-lead mse layout for a 2-layer pcb gnd v1 v2 out ltc4420 c out gnd gnd c1 c2 4419 f12 layout, choose c1 to be 2.2 f, which is ~1/5 th of c out to suppress inductive transients. also snub c1 with a 0.5 resistor to prevent ringing. layout consideration make power and ground traces as wide as possible. place bypass capacitors, snubbers and tvs devices as close to the pin as possible to reduce power path resistance and parasitic inductance. these result in smaller overvoltage transients and improved overvoltage protection. place resistive dividers close to the pins to improve noise im - munity. use a 4- layer board if possible with layer 2 as dedicated gnd and solder the exposed pad to a large pcb gnd trace for better heat dissipation. a partial layout for a 2-layer pcb is shown in figure 12. ltc 4420 4420f
19 for more information www.linear.com/ltc4420 a pplica t ions i n f or m a t ion figure 13. maximum allowed c out vs input voltage for different t a typical a pplica t ions battery backup with interface to low voltage logic thermal protection and maximum c out depending on the difference between input and output voltages, the ltc4420s internal power dissipation can be high when operating in current limit mode. this usually occurs when a large c out is being charged either during initial power up or when out switches over to a higher supply. the situation is worsened if there is a dc load on out, as this reduces the current available to charge c out . in such cases, self heating can cause power path turn-off due to activation of the thermal protection circuitry. the power path is reactivated when die temperature drops to a safe value. this process can repeat indefinitely if c out is discharged fully by load current i out in the interval when the power path is off. maximum allowed c out to prevent activation of the thermal protection circuit depends on several factors such as input supply and output voltages, starting ambient temperature, heat dissipation in the pcb and dc output current. choose c out < 500 f if possible. if a larger c out is necessary, use figure 13 to choose c out . also follow pcb layout guidelines to improve heat dissipation. r3 365k r sn1 0.5 5v to 18v wall adapter 3.6v to 18v backup switchover threshold: v1 < 4v (v1 falling) v1uv threshold: v1 < 4.5v (v1 falling) v2ok threshold: v2 < 3v (v2 falling) c out 10f r2 88.7k r6 1m r7 1m r8 1m r1 44.2k r4 150k r5 1m v1 out v2test v2dis cmpout1 v2ok 4420 ta02 adj cmp1 v2uv gndsw gnd ltc4420 v2 c1 10f c3 10f c2 10f in out ltc1763-3.3v shdn gnd v2ok v1uv 3.3v system r sn2 0.5 ltc 4420 4420f 10 15 20 100 1k 10k 60k c out (f) i load = 0 4420 f13 ?40c 25c 85c v in (v) 5
20 for more information www.linear.com/ltc4420 typical a pplica t ions triple voltage monitor supercap backup with supercap charging r3 1m r7 1m r8 1m r6 1m c out 10f r2 237k r1 121k r11 1.87m r12 301k r14 127k r13 12.1k 1.7v to 5.5v input r4 127k r5 1m v1 v2 out out v2ok v1uv v2test v2dis l1 3.3h 4.2v v2ok cmpout1 v2uv adj gndsw 4420 ta03 gnd ltc4420 cmp1 c2 940mf 940mf c1 10f c3 120pf c2: murata dmf325r5h474m3dta0 sw2 sw1 ltc3128 gnd v out rsenp rsens mid in prog maxv fb run switchover threshold: v1 < 4v (v1 falling) v1uv threshold: v1 < 4.4v (v1 falling) v2ok threshold: v2 < 3.5v (v2 falling) + r3 2m r10 2m r7 1m r8 1m c out 10f r1 191k r5 1m r4 59k 9v alkaline r9 113k + 14.8v li-ion v1 out out v2ok outuv cmp1 cmpout1 v2dis v2ok adj v2uv gndsw 4420 ta04 switchover threshold: v1 < 12v (v1 falling) v2ok threshold: v2 < 7v (v2 falling) outuv threshold: out < 7.5v (out falling) gnd ltc4420 v2 c1 10f c2 10f v2test ltc 4420 4420f
21 for more information www.linear.com/ltc4420 typical a pplica t ions early power failure warning with low battery indication prioritization with failsafe backup supply v1 adj cmp1 v2uv pfv1 v2 v2uv gndsw 4420 ta06 r3 1m r7 1m r8 1m c out 10f r2 75k r1 41.2k out out ds bat54 v2test v2ok cmpout1 v2dis ltc4420 gnd r5 1.37m pfv1 threshold: v1 < 10.6v (v1 falling) switchover threshold: v1 < 10v (v1 falling) v2uv threshold: v2 < 6v (v2 falling) 12v wall adapter coin cell 3v 2-cell li-ion 7.4v r4 95.3k c1 10f c2 10f + r sn1 0.5 r3 1m c out 10f pfv1 v2ok out r2 75k r1 41.2k l1, 10h v1 adj 4420 ta05 gnd ltc4420 cmp1 v2 sw2 sw1 bst2 bst1 v out v in comp fb run v cc snsgnd pwm ltc3111 c3 1f c5 0.1f 12v to other circuits c4 0.1f r13 1m r14 137k c8 10f 5v to 15v input c6 39pf c7, 1nf r12, 44.2k c1 22f r8 20k r10 2.21m r6 1m r7 1m r8 1m r11 158k c9 18pf r5 2m v2uv r4 66.5k gndsw out v2test v2dis cmpout1 v2ok c2 10f 4-cell 14.8v li-ion pfv1 , v1 power failure threshold: v1 < 10.6v (v1 falling) switchover threshold: v1 < 10v (v1 falling) v2ok threshold: v2 < 12v (v2 falling) + ltc 4420 4420f
22 for more information www.linear.com/ltc4420 p ackage descrip t ion please refer to http://www .linear.com/product/ltc4420#packaging for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd12) dfn 0106 rev a 0.23 0.05 pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline 0.45 bsc dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) ltc 4420 4420f
23 for more information www.linear.com/ltc4420 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/product/ltc4420#packaging for the most recent package drawings. msop (mse12) 0213 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev g) ltc 4420 4420f
24 for more information www.linear.com/ltc4420 ? linear technology corporation 2016 lt 0816 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4420 r ela t e d p ar t s typical a pplica t ion high efficiency backup part number description comments lt ? 1763 500ma, low noise micropower ldo regulators v in : 1.8v to 20v, 12-dfn, 8-so packages ltc2952 pushbutton powerpath controller with supervisor v in : 2.7v to 28v, on/off timers, 8kv hbm esd, tssop-20 and qfn-20 packages ltc 3103 15v, 300ma synchronous step-down dc/dc converter v in : 2.5v to 15v, dfn-10 and mse-10 packages LTC3129/LTC3129-1 15v, 200ma synchronous buck-boost dc/dc converter with 1.3a quiescent current v in : 1.92v to 15v, qfn-16 and mse-16 packages ltc3388-1/ltc3388-3 20v, 50ma high efficiency nanopower step-down regulator v in : 2.7v to 20v, dfn-10 and mse-10 packages ltc4411 2.6a low loss ideal diode in thinsot? internal 2.6a p-channel, 2.6v to 5.5v, 40a i q , sot-23 package ltc4412 36v low loss powerpath controller in thinsot 2.5v to 36v, p-channel, 11a i q , sot-23 package ltc4415 dual 4a ideal diodes with adjustable current limit dual internal p-channel, 1.7v to 5.5v, msop-16 and dfn-16 packages ltc4416 36v low loss dual powerpath controller for large pfets 3.6v to 36v, 35a i q per supply, msop-10 package ltc4417 3-channel prioritized powerpath controller triple p-channel controller, 2.5v to 36v, ssop-24 and qfn-24 packages ltc4355 positive high voltage ideal diode-or with supply and fuse monitors dual n-channel, 9v to 80v, so-16, msop-16 and dfn-14 packages ltc 4359 ideal diode controller with reverse input protection n-channel, 4v to 80v, msop-8 and dfn-6 packages r3 1m r7 1m r8 1m c out 10f c3 2.2f r2 237k r1 121k r5 1.37m r4 95.3k 5v wall adapter 2-cell 7.4v li-ion r12 1.1m r11 1.05m v1 out v2test v1uv v2uv cmpout1 v2ok v2dis run 5v adj cmp1 v2uv gndsw 4420 ta07 gnd ltc4420 v2 c6 10f c2 10f c1 10f run mppc vs1 vs2 v cc bst1 bst2 sw1 pwm gnd pgnd LTC3129-1 vs3 sw2 c4 22nf c5 22nf l1 3.3h v in out system r13 1m switchover threshold: v1 < 4v (v1 falling) v1uv threshold: v1 < 4.4v (v1 falling) v2uv threshold: v2 < 6v (v2 falling) r sn1 0.5 + ltc 4420 4420f

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